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MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
DESCRIPTION/FEATURES
*
* Serial I/O ..................................... 3 (CS controller, external clock)
* Noise filter ..................................................... built-in (in serial input pin and clock pin, 2 MHz sampling) * FLD display data ............................................. input * A-D conversion data ..................................... output * Command ....................................................... input Package ......................................................................... 36P2R-G Oscillation circuit ........... CR oscillation cirucit (external capacitor) * Oscillation frequency..................................... 2 MHz Power source voltage .................................................. 4.0 to 5.5 V
*
High-breakdown-voltage output port ......................................... 25 * Segment output ............................................ 8 to 20 * Digit output ................................................... 5 to 16 (Ports P0 to P2 are also used as normal output ports) * Output breakdown .................................. Vcc - 45 V * Output current ............... -18 mA (at DIG selecting), -7 mA (at SEG selecting) * Pull-down resistor .........................................built-in * Dimmer switch ............................................ 4 levels A-D converter ................................................... 8-bit ! 4 channels * Absolute accuracy ....................................... 3 LSB
* * *
PIN CONFIGURATION (TOP VIEW)
FLD10
FLD11
FLD12
FLD13
FLD14
FLD15 21 16 FLD19
FLD16 20 17 FLD18
FLD0
FLD1
FLD2
FLD3
FLD4
FLD5
FLD6
FLD7
FLD8
FLD9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
M35502AFP
10 11 12 13 14 15 18 FLD17 1 2 3 4 5 6 7 8 9
SCLK
FLD21
FLD24/P0
FLD23/P1
Package type: 36P2R-G
Fig.1 Pin configuration of M35502AFP
FLD22/P2
FLD20
SDATA
OSC
CS
VSS
AN3
AN2
AN1
AN0
VCC
19
VEE
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
FUNCTIONAL BLOCK
FLD15-FLD8
21 22 23 24 25 26 27 28
FLD7-FLD0
29 30 31 32 33 34 35 36
VEE
19
FLD16 20 FLD17 18 FLD18 17 FLD19 16 FLD20 15 FLD21 14 FLD22/P2 13 FLD23/P1 12 FLD24/P0 11 Memory address Transfer counter Display RAM Mode register Display control circuit
Command analytic circuit
Byte end
SDATA 1 SCLK 2 CS 3
Noise filter
Serial I/O
Noise filter
Trigger VCC 10 VSS 8
Clock generating circuit
Selector /A-D control circuit
A-D
9
4
5
6
7
OSC
Fig.2 Functional block diagram
AN3-AN0
2
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
PIN DESCRIPTION
Table 1 Pin description Pin VCC, VSS VEE OSC
____
Name Power source Pull-down power source Clock input Chip select Serial clock Serial input/ output Digit/Port Segment/Digit
Input
Output
Function * Apply voltage of 5 V to VCC, and 0 V to VSS. * Applies voltage supplied to pull-down resistors.
Input CMOS input CMOS input Noise filter CMOS input N-channel Noise filter open-drain P-channel open-drain P-channel open-drain
* Connect an external capacitor to this pin. * Serial transfer is possible by inputting "L" signal. * Pull-up resistor is built in. * Clock for serial transfer is input. * Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not. * Serial data is input/output. * In input mode, read a clock twice with 2 MHz sampling clock and judge if it is a noise or not. * Pin for ordinary output or digit output. * At reset this por t is set to VEE level through a pull-down resistor. * Pin for digit output or segment output. * At reset this por t is set to VEE level through a pull-down resistor.
CS SCLK SDATA
FLD24/P0 - FLD22/P2 FLD21- FLD0
PORT BLOCK
(1) Digit/Port pin Dimmer signal (Note) Data bus Digit data
Latch
(3) SDATA pin
Serial output V Serial input
Noise filter
VEE
(4) CS pin
(2) Segmen/Digit pin Dimmer signal (Note) Segment/Digit data
Latch
CS input
(5) SCLK pin V Serial clock input
Noise filter
VEE (6) A-D input A-D conversion input V High-breakdown-voltage P-channel transistor Not e : Dimmer signal is for setting the Toff time.
Fig.3 Port block diagram
3
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
COMMAND STYLE
b7 b6 b5 b4 b3 b2 b1 b0
Display data setting (Command 0)
1
1
1
a4
a3
a2
a1
a0
Digit start pin setting 0 0 0 0 : FLD18 0 0 0 1 : FLD17 0 0 1 0 : FLD16 0 0 1 1 : FLD15 0 1 0 0 : FLD14 0 1 0 1 : FLD13 0 1 1 0 : FLD12 0 1 1 1 : FLD11 1 0 0 0 : FLD10 1 0 0 1 : FLD9 1 0 1 0 : FLD8 Serial data transfer setting 1 : 3-byte transfer 0 : 4-byte transfer
Display state setting (Command 1)
1
1
0
M4 M3 M2 M1 M0
Display ON or OFF setting 1 : ON 0 : OFF Display duty setting 1 1 : 15/16 1 0 : 6/16 0 1 : 4/16 0 0 : 3/16 DIG/PORT switch setting (Note ) 0 0 : P0 output of command 3 valid 0 1 : P0, P1 output of command 3 valid 1 0 : P0, P1, P2 output of command 3 valid 1 1 : All port is set as DIG.
Number of timing selecting (Command 2)
1
0
1
-
T3
T2
T1
T0
Number of timing setting 0 0 0 0 : T16 0 0 0 1 : T15 0 0 1 0 : T14 0 0 1 1 : T13 0 1 0 0 : T12 0 1 0 1 : T11 0 1 1 0 : T10 0 1 1 1 : T9 1 0 0 0 : T8 1 0 0 1 : T7 1 0 1 0 : T6 1 0 1 1 : T5
Port data setting (Command 3)
1
0
0
-
-
p2
p1
p0
P2-P0 output data
N ote : DIG/PORT switch setting becomes valid when command 3 (port data setting) is accepted. When command 3
is not used, set "112" to these bits.
Fig.4 Command style
4
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
SERIAL I/O PROTOCOL
Byte protocol CS
CLK b0 b1 b2 b3 b4 b5 b6 b7
SDATA(input) SDATA(output)
b0
b1
b2
b3
b4
b5
b6
b7
Note: SDATA is in high-impedance state during CS signal is "H".
Command protocol Display data setting (Command 0) CS CLK SDATA(input)
Command 0 Data 1 Data 2 Data i
Notes 1: The serial data which is transmitted after executing command 0 is recognized as a display data. 2: Set the CS signal to "H" level after transferring a display data.
Other setting except display data setting (Command 1 to 3) CS CLK SDATA(input)
Fig.5 Serial I/O protocol
Command
5
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
SERIAL COMMUNICATION FORMAT (DISPLAY DATA, A-D OUTPUT)
When using 25 high-breakdown-voltage ports (segment + grid) (4-byte transfer) CS CLK SDATA
X AD 0 AD 1 AD 2 AD 3
C om m and 0
FLD 0-7
FLD
8-15
FLD
16-23
FLD 24
FLD
16-23
FLD 24
FLD 0-7
FLD
8-15
FLD
16-23
FLD 24
AD valid data Output mode
Tn Input mode
T2
T1
The SDATA pin becoms output mode from after the CS pin falling until the 5th byte of serial data. The SDATA becomes command input mode from the 6th byte of serial data.
When using 24 high-breakdown-voltage ports (segment + grid) (3-byte transfer) CS CLK SDATA
X AD 0 AD 1 AD 2 AD 3
C om m and 0
FLD 0-7
FLD
8-15
FLD
16-23
FLD 0-7 Tn-1
FLD 0-7
FLD
8-15
FLD
16-23
FLD 0-7
FLD
8-15
FLD
16-23
AD valid data Output mode
Tn
T2
T1
Input mode
The SDATA pin becoms output mode from after the CS pin falling until the 5th byte of serial data. The SDATA becomes command input mode from the 6th byte of serial data.
When using 16 high-breakdown-voltage ports (segment + grid) or less (3-byte transfer) CS CLK SDATA
X AD 0 AD 1 AD 2 AD 3 C om m and 0 FLD 0-7 FLD
8-15
Dummy data
FLD 0-7 Tn-1
FLD 0-7
FLD
8-15
Dummy data
FLD 0-7
FLD
8-15
Dummy data
AD valid data Output mode
Tn
T2 Input mode
T1
Transfer dummy data to the third byte of each timing. The SDATA pin becoms output mode from after the CS pin falling until the 5th byte of serial data. The SDATA becomes command input mode from the 6th byte of serial data.
Fig.6 Serial communication format
6
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
FLD DISPLAY TIMING
Tn Tn-1 T1 Tn Tn-1
Gn Gn-1
G1 Segment output
Tdisp
Tscan=0ns
Digit Tdisp = 384 s (oscillation frequency f(OSC) = 2.0 MHz) Toff = 312 s (3/16 ! Tdisp) 288 s (4/16 ! Tdisp) 240 s (6/16 ! Tdisp) 24 s (15/16 ! Tdisp) Tdisp
Segment Toff
Fig.7 FLD display timing diagram
SEGMENT/DIGIT SETTING EXAMPLE
Grid: 5 S egm ent: 8 Grid: 7 Grid: 10 S egm ent: 8 S egm ent: 8 Grid: 7
Segm ent:18
PORT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Fig.8 Segment/Digit setting example
FLD FLD0 FLD1 FLD2 FLD3 FLD4 FLD5 FLD6 FLD7 FLD8 FLD9 FLD10 FLD11 FLD12 FLD13 FLD14 FLD15 FLD16 FLD17 FLD18 FLD19 FLD20 FLD21 FLD22 FLD23 FLD24
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 GRID5 GRID4 GRID3 GRID2 GRID1
SEG1 SEG1 SEG2 SEG2 SEG3 SEG3 SEG4 SEG4 SEG5 SEG5 SEG6 SEG6 SEG7 SEG7 SEG8 SEG8 GRID7 GRID10 GRID6 GRID9 GRID5 GRID8 GRID4 GRID7 GRID3 GRID6 GRID2 GRID5 GRID1 GRID4 GRID3 GRID2 GRID1
P2 P1 P0
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 GRID7 GRID6 GRID5 GRID4 GRID3 GRID2 GRID1
7
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
BIT ALLOCATION FOR DISPLAY RAM
ADDRESS b7 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16
FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD FLD 23 22 21 FLD FLD FLD 15 14 13 FLD FLD FLD 7 6 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD FLD FLD 23 22 21 20 FLD FLD FLD FLD 15 14 13 12 FLD FLD FLD FLD 4 7 6 5 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD FLD FLD FLD 23 22 21 20 19 FLD FLD FLD FLD FLD 15 14 13 12 11 FLD FLD FLD FLD FLD 7 6 5 4 3 FLD FLD 18 17 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 18 FLD 10 FLD 2 FLD 17 FLD 9 FLD 1
b0
FLD 24 FLD 16 FLD 8 FLD 0 FLD 24 FLD 16
b7 2016 2116 T1 2216 2316 2416 2516 T2 2616 2716 2816 2916 T3 2A16 2B16 2C16 2D16 T4 2E16 2F16 3016 3116 T5 3216 3316 3416 3516 T6 3616 3716 3816 3916 T7 3A16 3B16 3C16 3D16 T8 3E16 3F16
FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD 18 17 FLD FLD 10 9 FLD FLD 2 1 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD 18 17 FLD FLD 10 9 FLD FLD 2 1 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD FLD 18 17 FLD FLD 10 9 FLD FLD 2 1 FLD 23 FLD 15 FLD 7 FLD 22 FLD 14 FLD 6 FLD 21 FLD 13 FLD 5 FLD 20 FLD 12 FLD 4 FLD 19 FLD 11 FLD 3 FLD 18 FLD 10 FLD 2 FLD 17 FLD 9 FLD 1
b0
FLD 24 FLD 16 FLD 8 FLD 0 FLD 24 FLD 16 FLD 8 FLD 0 FLD 24 FLD 16 FLD 8 FLD 0 FLD 24 FLD 16 FLD 8 FLD 0 FLD 24
T9
FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 0 2 1
T10
T11
T12
FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0 FLD 24 FLD FLD FLD 18 17 16 FLD FLD FLD 10 9 8 FLD FLD FLD 2 1 0
T13
T14
T15
T16
Fig.9 Bit allocation for display RAM
8
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
CLOCK GENERATING CIRCUIT
Oscillating circuit is built up by connecting a capacitor between pins OSC and VSS. When supplying a clock externally, input it to the OSC pin.
OSC
OSC
External oscillation circuit
COSC
VCC VSS
Fig.10 CR generating circuit
Fig.11 External clock input circuit
HANDLING OF UNUSED PINS
Handle unused pins as the follow. Table 2 Handling of unused pins Pin Segment Digit Analog input Open Open Connect to VCC or VSS through a resistor. Handling
POWER-ON RESET
Reset can be performed automatically during power on (power-on reset) by the built-in power-on reset circuit.
VDD
Reset state
Internal reset signal
Poweron
Reset released
Fig.12 Power-on reset
9
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VEE VI VI VO Parameter Power source voltage Pull-down power source voltage Input voltage AN0 - AN3 __ Input voltage CS, SDATA, SCLK Output voltage FLD0 - FLD24 Conditions * All voltage are based on VSS. * Output transistors are cut off. Ratings -0.3 to 6.5 VCC-45 to VCC+0.3 -0.3 to VCC+0.3 -0.3 to VCC+0.3 VCC-45 to VCC+0.3 VCC-50 to VCC+0.3 Unit V V V V V
VO Pd Topr Tstg
Output voltage
SDATA
Power dissipation Operating temperature Storage temperature
* A waveform: 450 s or more frequency and 30 s or less pulse width. * Connect only capacitor load (CL = 200pF). * All voltage are based on VSS. * Output transistors are cut off. Ta = 25 C
-0.3 to VCC+0.3 600 -20 to 85 -40 to 125
V mW C C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VSS VEE VIH VIL Parameter Power source voltage Power source voltage Pull-down power source voltage __ "H" input voltage CS, SCLK, SDATA __ "L" input voltage CS, SCLK, SDATA
(VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Min. 4.0 VCC-38 0.75VCC 0 Limits Typ. 5.0 0 Max. 5.5 VCC VCC 0.25VCC Unit V V V V V
RECOMMENDED OPERATING CONDITIONS
Symbol IOH(peak) IOH(avg) IOH(peak) IOH(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) f(OSC) f(SCLK) Parameter
(VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Min. (Note 1) (Note 2) (Note 2) (Note 3) (Note 3) (Note 4) 1.4 2.0 250 Limits Typ. Max. -240 -120 -40 -20 10 -18 -7 5.0 2.6 Unit mA mA mA mA mA mA mA mA MHz kHz
"H" total peak output current FLD0 - FLD24 "H" total average output current FLD0 - FLD24 "H" peak output current FLD0 - FLD24 (at DIG selecting) "H" peak output current FLD0 - FLD24 (at SEG selecting) "L" peak output current SDATA "H" peak output current FLD0 - FLD24 (at DIG selecting) "H" average output current FLD0 - FLD24 (at SEG selecting) "L" average output current SDATA Clock input oscillation frequency Serial I/O external clock frequency
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: When the oscillation frequency has a 50 % duty cycle.
10
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
ELECTRICAL CHARACTERISTICS
Symbol VOH VOL VT+ -- VT- IIH IIL Parameter "H" output voltage "L" output voltage Hysteresis "H" input current "L" input current
(VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Test conditions IOH = -18 mA IOH = -7 mA IOL = 5 mA VCC = 5.0 V VI = VCC VI = VSS Min. VCC-2.0 VCC-2.0 Limits Typ. Max. Unit V V V V A A A A A
ILOAD
Output load current
DIG output SEG output SDATA ____ SDATA, SCLK, CS ____ SDATA, SCLK, CS SDATA, SCLK ____ CS OSC FLD0 - FLD24
2.0 0.5 5.0 -5.0 -500 -4.0 500
ILEAK
Output leakage current
FLD0 - FLD24
VEE = VCC-36 V VOL = VCC Output transistors "off" VEE = VCC-38 V VOL = VCC-38 V Output transistors "off"
250
750
-10
A
ELECTRICAL CHARACTERISTICS
Symbol VRAM ICC Parameter RAM hold voltage Power source current
(VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Test conditions When clock is stopped VCC = 5 V, f(XIN) = 2.0 MHz Output transistors "off" at A-D converter operating Min. 2.0 Limits Typ. 1.5 Max. 5.5 2.5 Unit V mA
A-D CONVERTER CHARACTERISTICS
Symbol -- -- Tconv VIA IIA RLADDER Parameter
(VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Test conditions Min. Limits Typ. Max. 8 3 100 VCC 5.0 Unit Bits LSB
tc(OSC)
Resolution Absolute accuracy (excluding quantization error) Conversion time Analog input voltage Analog port input current Ladder resistor
VCC = 5.12 V 0 0.5 35
V A k
11
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
TIMING REQUIREMENTS (VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted)
Symbol tc(OSC) twH(OSC) twL(OSC) tc(SCLK) twH(SCLK) twL(SCLK) tsu(SDATA-SCLK) th(SCLK-SDATA) __ tsu(CS) __ th(CS) tre(SCLK) Parameter Reset input "L" pulse width Clock input "H" pulse width Clock input "L" pulse width Serial clock input cycle time (Note) Serial clock input "H" pulse width (Note) Serial clock input "L" pulse width (Note) Serial input setup time (Note) Serial input hold time (Note) Serial input setup time Serial input hold time Serial clock interval time Min. 384 120 120 5 2 3 2 3 50 tc(OSC) 50 tc(OSC) 50 tc(OSC) Limits Typ. Max. Unit ns ns ns CLKs CLKs CLKs CLKs CLKs ns ns ns
Note: The unit means a number of noise filter sampling clock (tc(OSC)).
SWITCHING CHARACTERISTICS
Symbol td(SCLK-SOUT) tv(SCLK-SOUT) tr(Pch) COSC Parameter
(VCC = 4.0 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Test conditions Min. 0 CL = 100pF VEE = VCC-36 V 1.8 18 80 Limits Typ. Max. 3 Unit CLKs ns
Serial I/O output delay time (Note 1) Serial I/O output valid time High-breakdown-voltage P-channel open-drain output rising time External capacitor size (Note 2)
s
pF
Note 1: The unit means a number of noise filter sampling clock (tc(OSC)). 2: An external capacitor size varies with a mounted condition.
Measuring condition: Ta = 25C, Vcc = 5.0 V)
Frequency - External capacitor size 3.0 Frequency f(OSC) [MHz] 2.5 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 70 80 External capacitor size COSC (pF)
Fig. 13 Standard characteristic example of f(OSC)-COSC
12
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
Serial I/O clock output port
P-channel output port
RL
CL VEE
CL
Fig.14 Output switching characteristics measurement circuit diagram
CS SCLK
tsu(CS) trec(SCLK) th(CS)
tC(SCLK) tWL(SCLK) tWH(SCLK) 0.8VCC
SCLK
0.2VCC tsu(SDATA-SCLK)
th(SCLK-SDATA)
SDATA (input)
td(SCLK-SDATA)
0.8VCC 0.2VCC tv(SCLK-SDATA)
SDATA (output)
Fig.15 Timing diagram
13
MITSUBISHI LINEAR IC's
M35502AFP
FLD CONTROLLER
PACKAGE OUTLINE
36P2R-G
EIAJ Package Code SSOP36-P-450-0.80
36
Plastic 36pin 450mil SSOP
JEDEC Code -- Weight(g) 0.53
19
Lead Material Alloy 42
e
b2
HE
E
e1
F
Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.3 -- -- 0.2 0.1 0 -- 2.0 -- 0.4 0.3 0.25 0.22 0.15 0.10 15.2 15.0 14.8 8.6 8.4 8.2 -- 0.8 -- 10.7 10.4 10.1 0.7 0.5 0.3 -- 1.0 -- -- 0.7 -- -- -- 0.85 0.15 -- -- 0 -- 10 -- 0.5 -- -- 11.43 -- -- -- 1.27
Symbol
1 18
A
G
D A2 e y
b
A1
c z Z1 Detail G Detail F
A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2
L1
14
L
I2
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
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* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
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(c) 2000 MITSUBISHI ELECTRIC CORP. New publication, effective Apr. 2000. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 1.1 First Edition Font error is revised. Revision Description
M35502AFP DATA SHEET
Rev. date 990726 000414
(1/1)

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